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Installation and Operation Manual Chapter 1 Introduction
Egate-100 Ver. 4.0 Functional Description 1-9
Incoming traffic from the Ethernet ports is processed by the Network processor,
which performs bridging, forwarding and QoS based queuing, which results in an
egress bridge to a logical port. The packets are marked with a bridge port ID and
forwarded over the high speed bus to the FPGA. The FPGA maps the packets of
each bridge port to the associated E1/T1 group according to the associated
encapsulation method.
Figure
1-3
illustrates the work flow and
Figure
1-4
illustrates the corresponding
hardware blocks inside Egate-100.
The FPGA is responsible for the HDLC/GFP encapsulation including CRC calculation
and zero bit insertion. The FPGA then maps each of these flows into the right
bundle and forwards it over the TDM bus to the SDH/SONET mapper.
In the opposite direction, the same process takes place with the packet being
transferred to the Ethernet port. Local switching between two virtual ports is
possible.
In case of an MLPPP bundle (nxE1/T1 bundle), the network processor is
responsible for the implementation of the appropriate inverse multiplexer
scheme/buffer. In case of GFP and GFP bonding, the FPGA handles the GFP
encapsulation and bonding unlike the MLPPP case where the network processor
performs the bonding.
STM-1/OC-3 Mapping
The SDH/SONET port supports STM-1/OC-3 over optical interface. The optical
interface can be either single-mode short-haul according to G.957 S 1.1, single
mode long haul according to G.957 L 1.1, or multimode according to ANSI T1 646.
Two STM-1/OC-3 ports support APS, to ensure that one is available at all times.
Egate-100 operates in either SDH or SONET mode to support different framing
and mapping parameters.
Two mapping schemes are presented:
E1 over STM-1 (SDH path)
T1 over OC-3 (SONET path).
STM-1 Mapping
The following figure illustrates the mapping of E1s over SDH.
Figure
1-5. STM-1 / AU-4 / VC-4 / TUG-3s / TUG-2s / TU-12s / VC-12s /E1s
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